Design Recipes for FPGAs - Edition 2 - By Peter Wilson Elsevier Inspection Copies

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Design Recipes for FPGAs,

Edition 2 Using Verilog and VHDL

By Peter Wilson

Publication Date: 23 Sep 2015

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Design Recipes for FPGAs provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement.

Key Features

Examples are rewritten and tested in Verilog and VHDL
Describes high-level applications as examples and provides the building blocks to implement them, enabling the student to start practical work straight away
Singles out the most important parts of the language that are needed for design, giving the student the information needed to get up and running quickly

About the author

By Peter Wilson, University of Bath and Integra Designs Ltd., UK

Part 1: Overview

Introduction

Chapter 1: Introduction

Abstract
1.1 Overview
1.2 Verilog vs. VHDL
1.3 Why FPGAs?
1.4 Summary

Chapter 2: An FPGA Primer

Abstract
2.1 Introduction
2.2 FPGA Evolution
2.3 Programmable Logic Devices
2.4 Field Programmable Gate Arrays
2.5 FPGA Design Techniques
2.6 Design Constraints using FPGAs
2.7 Development Kits and Boards
2.8 Summary

Chapter 3: A VHDL Primer: The Essentials

Abstract
3.1 Introduction
3.2 Entity: Model Interface
3.3 Architecture: Model Behavior
3.4 Process: Basic Functional Unit in VHDL
3.5 Basic Variable Types and Operators
3.6 Decisions and Loops
3.7 Hierarchical Design
3.8 Debugging Models
3.9 Basic Data Types
3.10 Summary

Chapter 4: A Verilog Primer: The Essentials

Abstract
4.1 Introduction
4.2 Modules
4.3 Connections
4.4 Wires and Registers
4.5 Defining the Module Behavior
4.6 Parameters
4.7 Variables
4.8 Data Types
4.9 Decision Making
4.10 Loops
4.11 Summary

Chapter 5: Design Automation of FPGAs

Abstract
5.1 Introduction
5.2 Simulation
5.3 Libraries
5.4 std_logic Type Definition
5.5 Synthesis
5.6 RTL Design Flow
5.7 Physical Design Flow
5.8 Place and Route
5.9 Timing Analysis
5.10 Design Pitfalls
5.11 Summary

Chapter 6: Synthesis

Abstract
6.1 Introduction
6.2 Numeric Types
6.3 Wait Statements
6.4 Assertions
6.5 Loops
6.6 Some Interesting Cases Where Synthesis May Fail
6.7 What Is Being Synthesized?
6.8 Summary

Part 2: Introduction to FPGA Applications

Introduction

Chapter 7: High Speed Video Application

Abstract
7.1 Introduction
7.2 The Camera Link Interface
7.3 Getting Started
7.4 Specifying the Interfaces
7.5 Defining the Top Level Design
7.6 System Block Definitions and Interfaces
7.7 The Camera Link Interface
7.8 The PC Interface
7.9 Summary

Chapter 8: Simple Embedded Processors

Abstract
8.1 Introduction
8.2 A Simple Embedded Processor
8.3 A Simple Embedded Processor Implemented in VHDL
8.4 A Simple Embedded Processor Implemented in Verilog
8.5 Soft Core Processors on an FPGA
8.6 Summary

Part 3: Designer’s Toolbox

Introduction

Chapter 9: Digital Filters

Abstract
9.1 Introduction
9.2 Converting S Domain to Z Domain
9.3 Implementing Z Domain Functions in VHDL
9.4 Basic Low Pass Filter Model
9.5 Implementing Z Domain Functions in Verilog
9.6 Finite Impulse Response Filters
9.7 Infinite Impulse Response Filters
9.8 Summary

Chapter 10: Secure Systems

Abstract
10.1 Introduction to Block Ciphers
10.2 Feistel Lattice Structures
10.3 The Data Encryption Standard (DES)
10.4 Advanced Encryption Standard
10.5 Summary

Chapter 11: Memory

Abstract
11.1 Introduction
11.2 Modeling Memory in HDLs
11.3 Read Only Memory
11.4 Random Access Memory
11.5 Synchronous RAM
11.6 Flash Memory
11.7 Summary

Chapter 12: PS/2 Mouse Interface

Abstract
12.1 Introduction
12.2 PS/2 Mouse Basics
12.3 PS/2 Mouse Commands
12.4 PS/2 Mouse Data Packets
12.5 PS/2 Operation Modes
12.6 PS/2 Mouse with Wheel
12.7 Basic PS/2 Mouse Handler VHDL
12.8 Modified PS/2 Mouse Handler VHDL
12.9 Basic PS/2 Mouse Handler in Verilog
12.10 Summary

Chapter 13: PS/2 Keyboard Interface

Abstract
13.1 Introduction
13.2 PS/2 Keyboard Basics
13.3 PS/2 Keyboard Commands
13.4 PS/2 Keyboard Data Packets
13.5 PS/2 Keyboard Operation Modes
13.6 Summary

Chapter 14: A Simple VGA Interface

Abstract
14.1 Introduction
14.2 Basic Pixel Timing
14.3 Image Handling
14.4 A VGA Interface in VHDL
14.5 A VGA Interface in Verilog
14.6 Summary

Chapter 15: Serial Communications

Abstract
15.1 Introduction
15.2 Manchester Encoding and Decoding
15.3 Implementing the Manchester Encoding Scheme using VHDL
15.4 Implementing the Manchester Encoding Scheme using Verilog
15.5 NRZ (Non-Return-to-Zero) Coding and Decoding
15.6 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
15.7 RS-232
15.8 Universal Serial Bus
15.9 Summary

Part 4: Optimizing Designs

Introduction

Chapter 16: Design Optimization

Abstract
16.1 Introduction
16.2 Techniques for Logic Optimization
16.3 Improving Performance
16.4 Critical Path Analysis
16.5 Summary

Chapter 17: Behavioral Modeling in using HDLs

Abstract
17.1 Introduction
17.2 How to Go from RTL to Behavioral HDL Descriptions
17.3 Implementing the Behavioral Model using VHDL
17.4 Implementing the Behavioral Model using Verilog
17.5 Summary

Chapter 18: Mixed Signal Modeling

Abstract
18.1 Introduction
18.2 Basic Modeling Approach for VHDL-AMS
18.3 Introduction to VHDL-AMS
18.4 VHDL-AMS Analog Pins: TERMINALS
18.5 Mixed Domain Modeling
18.6 VHDL-AMS Analog Variables: Quantities
18.7 Simultaneous Equations in VHDL-AMS
18.8 A VHDL-AMS Example: A DC Voltage Source
18.9 A VHDL-AMS Example: Resistor
18.10 Differential Equations in VHDL-AMS
18.11 Mixed-Signal Modeling with VHDL-AMS
18.12 A Basic Switch Model
18.13 Basic VHDL-AMS Comparator Model
18.14 Multiple Domain Modeling
18.15 Introduction to Verilog-AMS
18.16 Verilog-AMS: Analog ports
18.17 Mixed Domain Modeling in Verilog-AMS
18.18 Verilog-AMS Analog Variables
18.19 Verilog-AMS Analog Equations
18.20 A Verilog-AMS Example
18.21 Differential Equations in Verilog-AMS
18.22 Mixed Signal Modeling with Verilog-AMS
18.23 Multiple Domain Modeling using Verilog-AMS
18.24 Summary

Chapter 19: Design Optimization Example: DES

Abstract
19.1 Introduction
19.2 The Data Encryption Standard
19.3 MOODS
19.4 Initial Design
19.5 Initial Synthesis
19.6 Optimizing the Datapath
19.7 Final Optimization
19.8 Results
19.9 Triple DES
19.10 Comparing the Approaches
19.11 Summary

Part 5: Fundamental Techniques

Introduction

Chapter 20: Latches, Flip-Flops, and Registers

Abstract
20.1 Introduction
20.2 Latches
20.3 Flip-Flops
20.4 Registers
20.5 Summary

Chapter 21: ALU Functions

Abstract
21.1 Introduction
21.2 Logic Functions in VHDL
21.3 Structural n-Bit Addition
21.4 Logic Functions in Verilog
21.5 Configurable n-Bit Addition
21.6 Two’s Complement
21.7 Summary

Chapter 22: Finite State Machines in VHDL and Verilog

Abstract
22.1 Introduction
22.2 State Transition Diagrams
22.3 Implementing Finite State Machines in VHDL
22.4 Implementing Finite State Machines in Verilog
22.5 Testing the Finite State Machine Model
22.6 Summary

Chapter 23: Fixed Point Arithmetic

Abstract
23.1 Introduction
23.2 Basic Fixed Point Types in VHDL
23.3 Fixed Point Functions in VHDL
23.4 Testing the VHDL Fixed Point Functions
23.5 Fixed Point Types in Verilog
23.6 Floating Point Types in Verilog
23.7 Summary

Chapter 24: Counters

Abstract
24.1 Introduction
24.2 Basic Binary Counter using VHDL
24.3 Simple Binary Counter using Verilog
24.4 Synthesized Simple Binary Counter
24.5 Shift Register
24.6 The Johnson Counter
24.7 BCD Counter
24.8 Summary

Chapter 25: Decoders and Multiplexers

Abstract
25.1 Decoders
25.2 Multiplexers
25.3 Summary

Chapter 26: Multiplication

Abstract
26.1 Introduction
26.2 Basic Binary Multiplication
26.3 VHDL Unsigned Multiplier
26.4 Synthesis of the Multiplication Function
26.5 Simple Multiplication using VHDL
26.6 Simple Multiplication using Verilog
26.7 Summary

Chapter 27: Simple 7-Segment (LCD) Displays

Abstract
27.1 Introduction
27.2 VHDL LCD Module Decoder
27.3 Verilog LCD Module Decoder
27.4 Summary

Bibliography

Introduction
Useful Texts for VHDL
Useful Texts for Verilog
Useful Texts for FPGAs
General Digital Design Books

ISBN: 9780080971292

Page Count: 392

Retail Price : £45.99

Grout: Digital Systems Design with FPGAs and CPLDs (Newnes, 2008). ISBN 9780750683975. Paperback, 784pp, $83.95/ £50.99. LTD sales 664.

Maxfield: Design Warrior's Guide to FPGAs (Newnes, 2004). ISBN 9780750676045. Paperback, 560pp, $65.95/ £39.99. LTD sales 7146.

Smith: FPGAs 101 (Newnes, 2010). ISBN 9781856177061. Paperback, 240pp, $44.95/ £27.99. LTD sales 220.

Embedded system development engineers, FPGA engineers, hardware and software engineers. Undergraduates and postgraduates studying an embedded system which focuses on FPGA design

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