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Electronic Design Automation,

Edition 1 Synthesis, Verification, and Test

Editors: Edited by Laung-Terng Wang, Yao-Wen Chang and Kwang-Ting (Tim) Cheng

Publication Date: 26 Feb 2009

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This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book.

Key Features

Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly
Includes comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence
Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products
Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes

About the author

Edited by Laung-Terng Wang, SynTest Technologies, Inc., Sunnyvale, CA, USA; Yao-Wen Chang, National Taiwan University, Taipai, Taiwan; and Kwang-Ting (Tim) Cheng, University of California, Santa Barbara, USA

Chapter 1: Introduction
Chapter 2: Fundamentals of CMOS Design
Chapter 3: Design for Testability
Chapter 4: Fundamentals of Algorithms
Chapter 5: Electronic System-Level Design and High-Level Synthesis
Chapter 6: Logic Synthesis in a Nutshell
Chapter 7: Test Synthesis
Chapter 8: Logic and Circuit Simulation
Chapter 9: Functional Verification
Chapter 10: Floorplanning
Chapter 11: Placement
Chapter 12: Global and Detailed Routing
Chapter 13: Synthesis of Clock and Power/Ground Networks
Chapter 14: Fault Simulation and Test Generation.

ISBN: 9780123743640

Page Count: 972

Retail Price (USD) :

Ashenden, The Designer's Guide to VHDL, 2e (MKP, '01), 759pp., $75.95, ISBN: 1558606742.
Wang, et. al., VLSI Test Principles and Architectures (MKP, July '06), 808pp., $64.95, ISBN: 0123705976
Bergeron, Writing Testbenches, 2e (Springer, '03), 512pp., $159.00, ISBN: 1402074018; bookscan sales of 747.

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Electronic Design Automation,

Editors: Edited by Laung-Terng Wang, Yao-Wen Chang and Kwang-Ting (Tim) Cheng

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About the author