RISC-V System-on-Chip Design - Edition 1 - By David Harris, James Stine, Ph.D., Sarah Harris and Rose Thompson Elsevier Educate

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RISC-V System-on-Chip Design,

Edition 1

By David Harris, James Stine, Ph.D., Sarah Harris and Rose Thompson

Publication Date: 15 May 2026

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RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons.

It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

Key Features

Covers detailed design for all components of a nontrivial microprocessor
Provides detailed explanations on the implementation of RISC-V microprocessors
Uses open-source SystemVerilog code and test cases for the entire processor, including single-issue and superscalar cores, multicore, all extensions (including multiplication/division, floating point, and atomic memory operations), and common peripherals
Enables users to build scripts to implement the processor on the open-source Skywater process

About the author

By David Harris, Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA; James Stine, Ph.D., School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, OK, USA; Sarah Harris, Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA and Rose Thompson

Preface
How to Use This Book
Acknowledgements
About the Authors
Foreword

01. A Brief History of Computer Design
02. Introduction to RISC-V
03. RISC-V Software Tool Flow
04. HDL Design Practices
05. Design Verification
06. Logic Synthesis
07. Pipelined Core
08. Privileged Operations
09. Bus Interface
10. Caches
11. Memory Management Unit
12. Load/Store Unit
13. Instruction Fetch Unit
14. Extensions: C (Compressed)
15. Extensions: M (Multiply and Divide)
16. Extensions: F/D/Q/Zfh/Zfa (Floating-Point)
17. Extensions: A (Atomic)
18. Extensions: Zb* and Zk* (Bit Manipulation and Cryptography)
19. Other Extensions
20. Peripherals
21. Benchmarking
22. Linux
23. FPGA Implementation
Appendix A Wally Synopsis
Appendix B Hitchhiker’s Guide to Linux
Appendix C Version Control using Git
Appendix D Tcl Book of Armaments
Appendix E Floating-Point Implementation
Bibliography
Index

ISBN: 9780323994989

Page Count: 600

Retail Price (USD) :

9780321547743; 9780130909961; 9781119481515

Senior-level elective or graduate courses in the field of computer processor design in most electrical or computer engineering or CS programs

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